PIC16F628A

On these pages, I will explain the hardware specification of PICF628. The contents of the explanation is the part which is different from PIC16F873. So, as for the basic specification, refer to PIC16F84A and PIC16F873. As for the detail specification, refer to PIC16F628.
PIC16F628 is PIC which has a lot of features than PIC16F84A. Those functions are the function which is adopted in PIC16F873. The program memory is 2K Words, the RAM memory is 224 bytes and the EEPROM is 128 bytes. It has three kinds of timers, Analog Digital converter, Universal communication port and so on. Also, it has one set of CCP.
Flash memory is used for PIC16F628 like PIC16F84A and PIC16F873. So, the program can be easily rewritten by the PIC programmer. This is very convenient. The instructions of the software are same as PIC16F84A and PIC16F873. The number of the pins is 18 pins like 84A.
RA0-7 : Input/Output port A
RB0-7 : Input/Output port B
AN0-3 : Analog input port
RX : USART Asynchronous Receive
TX : USART Asynchronous Transmit
DT : Synchronous Data
CK : Synchronous Clock
CCP1 : Capture In/Compare Out/PWM Out
OSC1/CLKIN : Oscillator In/Ecternal Clock In
OSC2/CLKOUT : Oscillator Out/Clock Out
MCLR : Master Clear ( Active low Reset ) Vpp : Programming voltage input
T0CKI : Clock input to Timer0
T1OSO : Timer1 oscillator output
T1OSI :Timer1 oscillator input
PGD : Serial programming data
PGC : Serial programming clock
PGM : Low voltage programinng input
INT : External interrupt
VDD : Positive supply for logic and I/O pins
Vss : Ground reference for logic and I/O pins

SFR of PIC16F628
The RAM register file of PIC16F628 is divided into four like PIC16F873. Each size is 128 bytes. SFR(Special Function Registers) are allocated at 32 bytes from the head of each bank. After the 33rd byte is the register area which is possible to use freely. However the area which can be used is different from 873.

CONFİGURATİON WORD
PIC16F628 has the special area to say Configuration Word in the program memory.
This word is mapped in program memory location 2007h. This address is beyond the user program memory space. This word can be accessed only during programming.
The following system requirements of PIC can be designated by the configuration word.




CP1,CP0 : Code Protection bits ( These differ from PIC16F84A or PIC16F873 )
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
11 : Program memory code protection off
10 : 0400h-07FFh code protected
01 : 0200h-07FFh code protected
00 : 0000h-07FFhcode protected


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CPD : Data Code Protection bit
1 : Data memory code protection off
0 : Data memory code protected


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LVP : Low Voltage Programming Enable
1 : RB4/PGM pin has PGM function, low voltage programming enabled
0 : RB4/PGM is digital I/O, HV on MCLR must be used for programming


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BODEN : Brown-out Detect Reset Enable bit
1 : BOD Reset enabled
0 : BOD Reset disabled


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MCLRE : RA5/MCLR pin function select ( This bit is newly provided for PIC16F628 )
1 : RA5/MCLR pin function is MCLR
0 : RA5/MCLR pin function is digital Input, MCLR internally tied to VDD


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PWRTE : Power-up Timer Enable bit
1 : PWRT disabled
0 : PWRT enabled


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WDTE : Watchdog Timer Enable bit
1 : WDT enabled
0 : WDT disabled


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FOSC2,FOSC1,FOSC0 : Oscillator Selection bits ( Functions are added )
111 : ER(External Resistor) oscillator:
CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN

110 : ER(External Resistor) oscillator:
I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN

101 : INTRC(Internal 4MHz OSC) oscillator:
CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

100 : INTRC(Internal 4MHz OSC) oscillator:
I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

011 : EC(External Clock In):
I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN

010 : HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001 : XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

000 : LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKI

Timer of PIC16F628
PIC16F628 has three kinds of timer. The specification of each timer is same as PIC16F873.


Timer 0

The specification of timer0 is same as PIC16F84A. It has following features.

8 bits timer/counter TMR0 ( It can count up to 255 )
Readable and Writable counter
8 bits software programmable prescaler
( Shared with watchdog timer. It can be used in either)
Selectable internal clock or external clock
Interrupt on overflow from FFh to 00h
Edge select for external clock ( Rising edge or falling edge )


As for the specification, refer to the specification of the timer (TMR0).


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Timer 1

The timer1 module is a 16 bits timer/counter consisting of two 8 bits registers( TMR1H and TMR1L ). Also it has prescaler. It can be selected four values.
The overflow interruption can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE of PIE register. The interruption occurs when the counter rolls over to 0000h from FFFFh.

There are a timer mode and a counter mode in timer1. The operating mode is determined by the clock select bit ( TMR1CS bit of T1CON register ). In case of TMR1CS is cleared, it works as Timer, and in case of TMR1CS is set, it works as Counter.



Timer mode
In timer mode, Timer1 increments every instruction cycle (FOSC/4). Timer1 can be enable/disable by setting/clearing control bit ( TMR1ON bit of T1CON register ). Also, timer1 has an internal reset input. This reset can be generated by either of two CCP modules.

When the timer1 oscillator is enabled by setting T1OSCEN bit of T1CON register. In the case, it connects a crystal oscillator with Pin 12 and pin 13. The oscillation frequency is possible to 200KHz. These pins combine the input/output pin of RB6 and RB7. However, the feature as the input/output pin is ignored. The setting of TRISC register is ignored too.

Counter mode
In counter mode, Timer1 increments on every rising edge of clock input.
When T1OSCEN bit of T1CON register is cleared, Timer1 increments on every rising edge of clock input on pin RB6/T1OSO/T1CKI( pin 12 ).
When T1OSCEN bit of T1CON register is set, Timer1 increments on every rising edge of clock input on pin RB7/T1OSI( pin 13 ).
After Timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. When started from the L level, the first rising edge isn't counted.
If T1SYNC bit of T1CON register is cleared, the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage.

In Capture and Compare mode of CCP, timer1 is used.
In case of the asynchronous counter mode, the counter can not be used for the capture or compare feature.
As for the operation of the CCP, refer to CCP feature of PIC16F873.



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Timer 2

Timer2 is an 8 bits timer with a prescaler and a postscaler and it has an 8 bits period register PR2 The input clock (Fosc/4) has a prescale option of 1:1, 1:4 or 1:16 selected by T2CKPS1 and T2CKPS0 bits of T2CON register. The match output of TMR2 goes through a 4 bits postscaler which gives a 1:1 to 1:16 scaling inclusive
Timer2 increments from 00h until it matches PR2 and then reset to 00h on the next increment cycle. Then timer2 repeats incrementation from 00h to the value of PR2. The PR2 register is initialized to FFh upon reset. The match output of TMR2 goes through a postscaler to generate a TMR2 interruption ( latched in flag bit TMR2IF of PIR register ). Timer2 can be shut off by clearing TMR2ON bit of T2CON register to minimize power consumption.

Timer 2 is used for the PWM feature of CCP mainly. It is used to control the period of the continuation pulse.
As for the operation of the CCP, refer to CCP feature of PIC16F873.
CCP feature of PIC16F628


The PIC16F873 has a special feature as CCP.
CCP is the initial of Capture/Compare/PWM(Pulse Width Modulation).
PIC16F873 has one CCP module.

Because a CCP function is the same as that of PIC16F873, so some part of pages for PIC16F873 are used in the following explanation.

Capture This is the function to capture the 16 bits value of timer1 register when an event occurs on pin RB3/CCP1.
This can be used for the measurement of the period time of the signal like the frequency counter and so on.
Compare This is the function to compare constantly the 16 bits value of timer1 register against the CCPR1 register value.
This is convenient when it makes interruption occur periodically.
PWM This is the function to make a periodic pulse generate.
This function is used to control an external circuit with changing a pulse duration (Duty).


The timer resource of the capture and compare is timer1 and the timer resource of PWM is timer2.

CCP1 register is comprised of two 8 bits registers : CCPR1L for low byte and CCPR1H for high byte. The CCP1CON register controls the operation of CCP1. The special event trigger is generated by compare match and will reset Timer1.


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Capture mode

In Capture mode, CCPR1H : CCPR1L captures the 16 bits value of the TMR1 register when an event occurs on pin RB3/CCP1. In Capture mode, the RB3/CCP1 pin should be configured as an input by setting the TRISC register. If the RB3/CCP1 pin is configured as an output, a write to the port can cause a capture condition.

An event is defined as follows. An event is selected by control bits CCP1M3:CCP1M0 of CCP1CON register.


CCP1M3-0 Event
0000 CCP off ( resets CCP1 module )
0100 Every falling edge
0101 Every rising edge
0110 Every 4th rising edge
0111 Every 16th rising edge


When a capture is made, the interrupt request flag bit CCP1IF of PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost.

Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use capture feature. In asynchronous counter mode, the capture operation may not work. When the capture mode is changed, a false capture interrupt may be generated, You should keep bit CCP1IE of PIE register clear to avoid false interrupts and should clear the flag bit CCP1IF of PIR1 register following any such change in operating mode.

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Compare mode

In Compare mode, the 16 bits CCPR1 register value is constantly compared against the TMR1 register pair valueWhen a match occurs, the following actions will be done by the definition of CCP1M3:CCP1M0 of CCP1CON register.


CCP1M3-0 Action
1000 Set output on match ( CCP1IF bit is set )
1001 Clear output on match ( CCP1IF bit is set )
1010 Remains unchanged on match ( CCP1IF bit is set )
1011 Trigger special event ( CCP1IF bit is set )
Remains unchanged on match
In case of CCP1, resets TMR1


In Compare mode, the RB3/CCP1 pin should be configured as an output by setting the TRISC register.
Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use compare feature. In asynchronous counter mode, the compare operation may not work.

For PWM operation, CCP1M3 and CCP1M2 bits of CCP1CON register should be set.


CCP1M3-0 Operation
11xx PWM mode


In PWM mode, the RB3/CCP1 pin should be configured as an output by setting the TRISC register.
The PWM period is specified by the value of the PR2 register, the clock oscillation period and the prescaler value of Timer2.
The PWM duty cycle( the output stays high ) is specified by the value of CCPR1L register, the clock oscillation period and the prescaler value of Timer2. The CCPR1L contains the eight MSbs and CCP1X:CCP1Y contains the two LSbs.
The shortest duty cycle is the period time of the oscillator. In case of 10MHz oscillator, it is 0.1 microseconds. The maximum PWM resolution of the duty cycle is 1024.
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. Also, if the value of PWM duty cycle register( CCPR1L+CCP1X+CCP1Y ) is set to zero, the CCP1 pin will not be set.

For the details about PWM period and PWM duty cycle, refer to the page of PIC16F873.


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PWM mode
In PWM(Pulse Width Modulation) mode, the CCP1 pin produces up to a 10 bits resolution PWM output
Asynchronous communication of PIC16F628 (USART)
On this page, I will explain about USART which is the communication port equipped with PIC16F628.
USART is the initial of Universal Synchronous Asynchronous Receiver Transmitter.
Because this function is equipped with PIC16F873, so some part of pages for PIC16F873 are used in the following explanation.

The USART can be used following communicate mode.
Asynchronous
Synchronous - Master
Synchronous - Slave ( full duplex )
( half duplex )
( half duplex )

Generally, in the communication of the USART, one data block is composed of 8 bits.
The USART module also has a multi-processor communication capability using 9-bit address detection.

On this page, I will explain about Asynchronous mode communication.


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About asynchronous communication

When doing a data communications, the condition of "0" and "1" to have let out from the side of the sending it must be able to be recognized in the receiving side. In the asynchronous communication, it puts a start bit to the head of the transferred data(8 bits or 9 bits) and it puts a stop bit at the end of the data. Recognition in the data block is done by it. The start bit is an L level and the stop bit is the signal of the H level.
The circuit of the condition not to transfer data is H level. When becoming an L level(Start bit) from this condition, the receiving side recognizes that the data transfer begins. After that, according to the signaling speed, the transfer of the data is done. The transfer of the block ends when a stop bit (H level) is detected last. A signaling speed is controlled by the timer which is independent in the sender and the receiving side. So, it isn't possible to do correct communication when there is an error in this timer.
In the asynchronous mode communication of USART, the RX port is used for receiving and the TX port is used for the transmission, so, it is possible to send and receive at the same time. (Full duplex)


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Designation of port
In the asynchronous mode, it uses RB2/TX/CK (pin 8) for the data transmission and RB1/RX/DT (pin 7) is used for the data receiving. The mode of the input/output of the TX port, the RX port must be set to the TRISC register to use a USART. Bit 2 of B port is set to output mode (0) and bit 1 is set to input mode (1).

To use RB1 and RB2 as the USART port, the SPEN bit of the RCSTA register must be made "1".

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Designation of Asynchronous mode

Asynchronous mode is designated by clearing bit SYNC of the TXSTA register.


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Designation of signaling speed

The signaling speed of the USART is controlled by BRG(Baud Rate Generator). BRG is used both the asynchronous and synchronous modes of the USART.
BRG is controlled by the SPBRG register. It is the register to control a free run timer with byte. In case of asynchronous mode, BRGH bit of the TXSTA register is used for the control of the signaling speed too.
When writing a value in the SPBRG register, BRG timer is reset.

The clock frequency of the PIC and signaling speed can be calculated by the following formula.
Mode Low-speed (BRGH=0) High-speed (BRGH=1)
Asynchronous
(SYNC=0) Fosc/( 64( X + 1 )) Fosc/( 16( X + 1 ))
Synchronous
(SYNC=1) Fosc/( 4( X + 1 ))

Fosc is the clock frequency of the PIC.
X is the value of SPBRG register. It is 0 to 255

For the details of the value of the SPBRG register, refer to "SFR explanation for PIC16F873(17)".

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Transmitter operation
When doing an asynchronous transmission with the USART, it makes the SPEN bit of the RCSTA register "1" and it makes RB2 port as TX port.
When loading a transmit data to the TXREG register, it is transferred to the TSR(Transmit Shift Register) by the hardware and it is transmitted from the TX port. The transmission of the data is done by setting the TXEN bit of the TXSTA register.
LSb(Least Significant bit) is transmitted first.
When the contents of the TXREG are sent to the TRS, the TXIF bit of the PIR1 register becomes "1" and the interruption occurs. But, the TX1E bit of the PIE1 register must become "1". This interruption means that the contents of the TXREG has been sent to the TSR and it becomes the condition that it is possible to load data in the TXREG. The data can be continuously transmitted if detecting this interruption and setting the following data to the TXREG.(Back to Back) The TXIF bit can not be cleared in software. The TXIF bit is cleared when data is loaded in the TXREG.
The TRMT bit of the TXSRA register is set to "1" when the data of the TSR register is transmitted. This bit doesn't have an interruption logic. So, to confirm the empty of the TSR register, you should poll TRMT bit periodically.
Because the TSR register is not mapped in data memory, you can not read/write the contents of this register directly. A signaling speed is controlled by BRG(Baud Rate Generator).
Parity is not supported by the hardware, but can be implemented in software ( and stored as the ninth data bit ). In the case, ninth bit as parity is transmitted by setting parity bit contents to the TX9D bit of the TXSTA register and setting the TX9 bit. The TX9D bit must be set before setting the data to TXREG. A transmission is started as soon as loading data in the TXREG. It isn't normally transmitted when the ninth bit isn't set to TX9D before it.
When clearing TXEN bit while transmitting data, a transmitter is reset and the RB2/TX/CK pin becomes a high impedance condition.


Steps to follow when setting up an Asynchronous Transmission
1. Initialize the SPBRG register for the appropriate baud rate.
If a high speed baud rate is desired, set bit BRGH.
2. Enable the asynchronous serial port by clearing SYNC bit of the TXSTA register and setting SPEN bit of the RCSTA register.
3. If interrupts are desired, then set enable bit TXIE of the PIE1 register.
4. If 9-bit transmission is desired, then set transmit bit TX9 of the TXSTA register.
5. Enable the transmission by setting bit TXEN of the TXSTA register.
In this point, the TXREG register is in the condition to write that is possible and TXIF bit of the PIR1 register becomes "1".
6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.
7. Load data to the TXREG register.
( Start transmission )

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Transmission time chart of 1 Word

Transmission time chart of the continuation transmission (Back to Back)

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Receiver operation
When doing an asynchronous transmission with the USART, it makes the SPEN bit of the RCSTA register "1" and it makes RB1 port as RX port.
The data which was received at the RX port is received with the RSR register through the Data recovery circuit. Data at the RX port is sampled three times to do the judgment of the H level or the L level. A received data is stored in the RSR register according to the signaling speed which is specified by the SPBRG register and the BRGH bit of the TXSTA register.
When detecting a stop bit, the contents of the RSR register are transferred to the RCREG register. The RCIF bit of the PIR1 register is set when data is stored in the RCREG register and the interruption occurs. To make interruption occur, the RCIE bit of the PIE1 register must be set beforehand.
The RCREG register is composed in two FIFO(First In First Out) buffers and can store data for 2 block. This is the protection when delay in the reading processing by the software. RCIF bit is read only bit and is cleared with the hardware when all RCREG registers are read.
If both RCREG registers are full(It isn't read) when the receiving completes with the RSR register, the OERR bit of the RCSTA register is set and the occurring of the overrun error is expressed. The data which was stored in the RSR register at this time is lost. Also, receiving operation isn't done. It clears the CREN bit of the RCSTA register once and it sets to return this condition normally again. By this operation, OERR bit is cleared.
The FERR bit of the RCSTA register is set when the frame error detects with the RSR register. The RX9D bit and the FERR bit which is stored in the RCSTA register are rewritten every time it receives data in 1 block. So, the FERR bit of the RCSTA register must be checked before reading the contents of the RCREG register. When receiving a normal frame behind the error frame, the information of FERR disappears. So, the normality of the received data can not be judged.

Steps to follow when setting up an Asynchronous Reception
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH of the TXSTA register.
2. Enable the asynchronous serial port by clearing bit SYNC of the TXSTA register and setting bit SPEN of the RCSTA register.
3. If interrupts are desired, then set enable bit RCIE of the PIE1 register.
4. If 9-bit reception is desired, then set bit RX9 of the RCSTA register.
5. Enable the reception by setting bit CREN of the RCSTA register.
6. Flag bit RCIF of the PIR1 register will be set when reception is complete and an interrupt will be generated if enable bit RCIE of the PIE1 register is set.
7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.
8. Read the 8-bit received data by reading the RCREG register.
9. If any error occurred, clear the error by clearing enable bit CREN of the RCSTA register.

Receiving time chart

This time chart shows the situation which the over-run occurs.
In usual operation, because the contents of RCREG are read by the interruption of RCIF, the over-run doesn't occur.

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Address detection

The 9th bit can be used for the address data detection. I don't understand a way of using address data.
The operation is as follows. This operation is effective in case of 9-bit transfer.
Set RX9 bit and ADDEN bit of the RCSTA register. In this way, only when the data of the 9th bit is "1", received data is stored in the RCREG register. The data that the 9th bit is "0" isn't stored.